The present invention relates to a control circuit for controlling an output buffer circuit coupled to an output side of a semiconductor memory which shows a commencement of an access operation when an address translation appears, wherein the output buffer circuit is formed on a semiconductor chip.
In the prior art, there was proposed a conventional control circuit for controlling an output buffer circuit to be used for a semiconductor memory such as static random access memory (SRAM) including CMOS circuits wherein the semiconductor memory shows memory access operations when receipt of an address input detection signal from an address translation detection circuit which detects an address input translation. This conventional control system has a configuration as illustrated in FIG. 1. An output buffer circuit 52 is coupled to an output control circuit 51 for receiving control signals which comprise active/inactive signals. When the output buffer circuit 52 receives the active signal, then the output buffer circuit 52 comes into an active state. When the output buffer circuit 52 receives the inactive signal, then the output buffer circuit 52 comes into an inactive state. The output control circuit 51 is designed to receive a chip enable signal for controlling the active/inactive states of the memory, an output enable signal for controlling enable/unable states of data output operations and a write enable signal for controlling a write operation into memory cells provided in the memory device. The output control circuit 51 receives the inputs of the chip enable signal, the output enable signal and the write enable signals and then performs logic processes to thereby output buffer control signals which will be transmitted into the output buffer circuit 52.
The output buffer is further coupled via a sense amplifier 53 to memory cells for receiving data stored in the memory cells through the sense amplifier 53. The sense amplifier 53 is designed to perform a detection and an amplification of fine signal levels as data stored in the memory cells so that the output buffer 52 receives the memory data with the amplified levels from the memory cells via the sense amplifier 53.
The output buffer circuit 52 performs, according to the output buffer control signal from the output control circuit, to raise a high voltage level of the digital signals from the memory cells via the sense amplifier 53 and subsequently outputs output data on an output terminal not illustrated of the output buffer circuit.
The above described output buffer circuit 52 and the control circuit 51 are engaged with the following problems. The output buffer circuit 52 in a high impedance state is changed so that the output buffer circuit 52 may often output a logic signal "0" corresponding to the previous address and subsequently output a logic signal "1" corresponding to a later address. In such case, a large current may rapidly flow thereby a noise is caused which provides an influence to the circuit performance thereby resulting in a malfunction of the of the circuit.
The above circuit configuration performs without any times necessary for the address access, namely the logic signal "0" with the ground voltage level is rapidly changed to another logic signal "1" with at least the same high voltage level as the power source voltage.
Recently, there has been promoted the increase in the number of bits thereby the number of output buffer circuits 52 is increased up to eight, sixteen or thirty two. When a number of output buffer circuits simultaneously show rapid inversions of the output signals from the logic signal "0" to another logic signal "1", then a considerably large and rapid current flow appears thereby an output signal noise and a power source noise may be generated. This results in the malfunction of the circuits.
To settle the above problems, it has been proposed to use a flip flop circuit for controlling operations of the output buffer circuit wherein the flip flop circuit shows set and reset operations according to control signals comprising an address translation detection signal and a read out signal detection signal so that the output buffer circuit is controlled between in the active state and in the inactive state. This conventional technique is disclosed in the Japanese laid-open patent application No. 63-292483. This conventional circuit configuration is illustrated in FIG. 2. In the circuit configuration, there is provided an address input translation detection circuit 61 designed to receive an address input and detect any address translations. There is further provided a readout detection circuit 62 designed to receive data stored in memory cells and detect the completion of the readout operations from the memory cells. A sense amplifier 63 is coupled to the read out detection circuit 62 for receiving read out detection data from the read out detection circuit 62 and amplifying the received read out detection data. There is further provided a flip flop circuit 64 coupled to the address translation detection circuit 61 for receiving the output data S as a set signal concerning the address translation from the address translation detection circuit 61 and also coupled to the read out detection circuit 62 for receiving the read out detection output signal R as a reset signal from the read out detection circuit 62. There is also provided an output control circuit 65 being coupled to the flip flop circuit 64 for receiving the output of the flip flop circuit 64. The output control circuit 65 is also designed to receive a chip enable signal "CE", an output enable signal "OE" and a write enable signal "WE" to thereby output the output control signals. There is also provided an output buffer circuit 66 which is coupled to the output control circuit 65 for receiving the output control signals for active/inactive states of the output buffer circuit. Namely, the output buffer circuit 66 is controlled by the output control signal from the output control circuit 65 between the active/inactive states. The output buffer circuit 66 in the active state may perform raising up the voltage level of the high level signal received from the sense amplifier 63 and then outputs the output data on the output terminal of the output buffer circuit 66.
FIG. 3 illustrates circuit configurations of the read out detection circuit 62, the flip flop circuit 64 and the output control circuit 65. The read out detection circuit 62 includes first and second sense amplifiers 71 and 72 which are connected in parallel to each other to the sense amplifier 62. Each of the first and second sense amplifiers 71 and 72 is coupled to a single pair of bit lines BL and BL coupled to the memory cell array for detecting a voltage difference between the paired bit lines and subsequent amplifications of the detected voltage difference so that the first and second sense amplifiers 71 and 72 show outputs which have inverted phases to each other. First and second sense lines SL and SL are coupled to the outputs D and D of the first and second sense amplifiers 71 and 72 respectively. A p-channel MOS transistor 73 is coupled between the first and second sense lines SL and SL for serving as an equalizer. An exclusive NOR gate 74 has two inputs coupled to the first and second sense lines SL and SL. The sense amplifier 63 is coupled to the first and second sense lines SL and SL.
The flip flop circuit 64 comprises first and second NOR gates 75 and 76. The first NOR gate 75 has two inputs, one of which is coupled to an output side of the address translation detection circuit 61 and another input is coupled to an output of the second NOR gate 76. The first NOR gate 75 has a single output coupled to the output control circuit 65. The second NOR gate 76 has two inputs, one of which is coupled to the output of the exclusive NOR gate 74 in the read out detection circuit 62 and another input is coupled to the output of the first NOR gate 75.
The output control circuit 65 comprises a NAND gate having four inputs, the first of which is for receiving the chip enable signal "CE" and the second is for receiving the output enable signal "OE" and further the third of which is for receiving the write enable signal "WE" as well as the fourth one is coupled to the output of the first NOR gate 75 and the first input of the second NOR gate 76. The NAND gate 65 has an output coupled to the output buffer circuit 66 for supplying the output control signal to the output buffer circuit 66.
FIG. 4 is a circuit diagram illustrative of the output buffer circuit 66 which includes p-channel and n-channel MOS transistors 81 and 82 which are coupled in series to each other between a power source line and a ground line GND and an output terminal is provided between the p-channel and n-channel MOS transistors 81 and 82. Gates of the p-channel and n-channel MOS transistors 81 and 82 are coupled to first and second logic circuits. The first logic circuit comprises a first inverter 83 having an output coupled to the gate of the p-channel MOS transistor 81 and a first NOR gate 85 having an output coupled to an input of the first inverter 83. The first NOR gate 85 has two inputs, one of which is coupled to the sense amplifier 63 and another input being coupled to an output of a third inverter 87 which has an input coupled to the output control circuit for receiving the output control signal. The second logic circuit comprises a second inverter 84 having an output coupled to the gate of the n-channel MOS transistor 82 and a second NOR gate 86 having an output coupled to an input of the second inverter 84. The second NOR gate 86 has two inputs, one of which is coupled to the sense amplifier 63 and another input being coupled to the output control circuit 65 for receiving the output control signal from the output control circuit 65.
FIG. 5 is a timing chart of the circuit illustrated in FIG. 3. When the chip enable signal "CE" is in the enable state, the address input is changed from "A" to "B" thereby the address translation detection circuit 61 generates a high level address translation detection output signal. As a result, the flip flop circuit 64 is set and then outputs a low level output signal thereby the output control circuit 65 generates a high level output signal. As a result, the output buffer circuit 66 comes into the inactive state wherein the output terminal of the output buffer circuit 66 is electrically floated and then, resulting in a high impedance state. The address translation detection output signal causes the memory access operation commenced. According to the address translation detection output signal, a sense line equalize signal EQ is generated thereby the transistor 73 turns ON for a time duration. As a result, data D and D of the sense lines SL and SL are equalized thereby the exclusive NOR gate 74 generates a low level output signal. According to the informations stored in the memory cell corresponding to the address "B", a voltage difference is generated between the single pair of the bit lines BL and BL. The sense amplifiers 71 and 72 amplify the voltage difference, wherein the outputs of the sense amplifiers 71 and 72 are complements of each other. The exclusive NOR gate 74 generates a high level output signal and thus the flip flop circuit 64 is reset. At this time, the flip flop circuit 64 generates a high level set output. In this case, if the output enable signal "OE" is in the high level and the write enable signal "WE" is also in the high level where the chip enable signal "CE" is already in the active level or the high level, then the output control circuit 65 generates the low level output signal thereby the output buffer circuit 66 comes into the active state. The output buffer circuit 66 is made active by synchronizing with the read out operation of the data from the memory cells corresponding to the input address "B" an access time t3 after the address translation thereby the output buffer circuit 66 outputs the data stored in the addressed memory cells.
With reference to the Japanese laid-open patent application No. 2-301098, in order to reduce the power for the output buffer circuit and the noise, the output buffer circuit further has a transistor for assessing the output level detector in driving the output level of the output stage. The additional transistor may add an additional driving ability except in the vicinity of a level thereby enabling a high speed output level transition and thus ensuring a high speed access time. In the vicinity of the level, the driving ability of the transistor is decreased according to the output signal from the output level detector to suppress a peak current, resulting in suppressions of any generations of noises on the power source line and the ground line.
The above measures to reduce the power source noise and the output noise is accomplished by causing the output to be in the high impedance state and subsequent change into the low level or the high level. The above measure may allow a problem with increase of the noise particularly when the number of bits is increased and almost all outputs are changed into the low level or the high level. Particularly when the output buffer circuit is positioned far from the ground terminal, the floating of the ground potential is increased. This may allow the influence of the noise.
Normally, the output of the output buffer circuit illustrated in FIG. 4 is received by a gate of a MOS transistor. FIG. 6 illustrates a load equivalent circuit. A capacitor 90 has one terminal being grounded and another terminal being coupled to the output terminal illustrated in FIG. 4 between the p-channel and n-channel MOS transistors 81 and 82. The capacitor 90 may store the data level just before the output buffer circuit comes into the high impedance state according to the output control signal. The data level just before the output buffer circuit comes into the high impedance state according to the output control signal is "1", the data level "1" is stored in the capacitor 90 even after the output buffer circuit comes into the high impedance state. On the other hand, the output buffer circuit comes free from the high impedance state and then outputs the data level "0", the capacitor 90 may allow the charge stored therein flows out thereby a temporary current flows out from the capacitor 90. When there are a large number of output buffer circuits and the load circuits, it may be possible that a considerable large current may flow.
Further, even the high speed access time is ensured, during which a large current flows thereby making it difficult to suppress the noise and increase of the necessary power. In the standby state, the standby current is increased by externally changing the voltage level of the output terminal, for which reason the circuit is not suitable for the static random access memory. In the output level detector, the invertors loaded to the output terminal Dout may often come into the operation by the potential variation of the output terminal even in the standby state.
Accordingly, the issues of the above described prior art to be solved may be regarded as the following four matters. First one is to prevent any generation of the noise due to the operations of the output buffer circuits to thereby prevent any malfunctions of the circuits due to the noise.
Second issue is to reduce the number of invalid transition operations of the output buffer circuits so as to reduce the generation of the noise thereby suppressing any increase of the demanded power.
Third one is to suppress any generation of the rapid large current flow generated by the same operations of a large number of the output buffer circuits.
Fourth one is to prevent any rapid large current flow when the output of the output buffer circuit is received by the gate of the MOS transistor.